The present invention refers to a method for high precision programming nonvolatile memory cells, with optimized programming speed.
As is known, at present nonvolatile memory cells, in particular flash memory cells, are programmed by biasing the gate terminal of the cell to be written (via a word line) at a first preset potential (e.g., 8-9 V), the drain terminal (via a bit line) at a second preset potential (e.g., 5 V), and the source terminal at ground. In this way, hot selectrons are injected, i e., electrons are trapped in the cell floating gate region and the cell threshold voltage is modified.
Injection of hot electrons is, by its very nature, non-controlled and nonrepeatable with precision. Consequently, at present programming is carried out supplying a plurality of programming pulses and reading the cell threshold voltage after each programming pulse (verify step) to verify whether the desired value has been reached and to decide whether to apply or not Her programming pulses.
Currently under study are techniques for storing high density digital data (able to supply more than eight levels). These techniques require the use of feedback circuits in the programming circuitry (which is intended to supply the programming pulses and carry out the verify read operation). These circuits, however, make the verify step slower and make programming (which may comprise, altogether, 70-100 verify steps) longer.
It is moreover known that, when a voltage (either constant or pulsed) is applied on the drain terminal of the cell to be programmed, and a linearly increasing (ramp) voltage is applied on its control gate terminal, after a certain time the threshold voltage varies according to the same slope as the ramp. In this connection, reference is made to the article by C. Calligaro, A. Manstretta, A. Modelli, G. Torelli, xe2x80x9cTechnological and design constraints for multilevel flash memoriesxe2x80x9d, Proceedings of International Conference on Electronic Circuits and Systems, Rodes, Greece, pp. 1003-1008.
Exploiting this correlation, it has already been proposed (see European Patent Application No. 97830566.2 dated Nov. 3, 1997, in the name of the present assignee, incorporated herein by reference) to calculate the time necessary for the cell to be programmed to reach the desired threshold voltage starting from an initial threshold value, when the slope of the voltage ramp applied is known, so as to eliminate intermediate verify steps.
In particular, in the above referred patent application, the control gate terminal is supplied with a discrete ramp voltage comprising a series of voltage pulses having a constant preset duration xcex94xcfx84 and increasing amplitude with constant increment xcex94V; consequently, the ramp has an average slope m=xcex94V/xcex94xcfx84.
Since, in equilibrium, the threshold voltage of the cells to be programmed increases with a slope equal to the average slope m, the method described in this patent calculates, and then applies in succession, the number of voltage pulses necessary for obtaining the desired threshold voltage increment, without carrying out verify operations after each pulse, thus making it possible to reduce the total number of verify steps.
It is moreover known that the programming precision depends upon the amplitude of the voltage increment or step xcex94V applied to each programming pulse (see, for example, the article by P. L. Rolandi, R. Canegallo, E. Chioffi, D. Gema, G. Guaitini, C. Issartel, A. Kramer, F. Lhermet, M. Pasotti xe2x80x9c1M-Cell 6b/cell Analog Flash Memory for Digital Storagexe2x80x9d, ISSCC98, S. Francisco, Session: Memory, pp. 334-335). Consequently, to increase programming precision (and hence the number of programmable levels in a single cell), it is necessary to reduce the amplitude of the steps. However, the duration of the programming pulses is constant, therefore it is necessary to reduce the average slope of the ramp and hence increase the time necessary for programming the memory cell, as may be seen in the plot of FIG. 1, which shows the successions of pulses having two different amplitudes xcex94V1 and xcex94V2, one of which is twice as great as the other, necessary for reaching a same final value VF of the control gate voltage, starting from a same initial value V0.
This disadvantage is all the more noticeable, the higher the final threshold voltage to be programmed, in that, in this case, it is necessary to apply a high number of pulses, and the read time is significantly lengthened. Consequently, when a high programming precision is required, programming becomes slow.
The aim of the present invention is to provide a programming method overcoming said drawback.